Modular digital computer systems are well known in which one or more central processing units and one or more input-output devices communicate with each other and with a main memory over a common bus. Various schemes have been used for controlling access to the common bus. For example, access to the bus may be provided by a scheme in which each unit is granted access in succession. Right of access is passed on from unit to unit around a closed loop. Under such system, no unit has priority over any other unit, but vacant chassis slots present a problem in maintaining the sequence. Other schemes have been developed in which access is granted on a first come, first serve basis, but this is not always a satisfactory priority solution since the more active units tend to crowd out the less active units.
An alternative bus arrangement has heretofore been proposed in which priority between units contending for access is resolved using a pre-assigned order of priority. In such a system the contending unit that has the highest priority number gains access to the bus. The priority arbitration is repeated whenever the bus becomes available. Such known systems require a master unit, usually the highest priority unit, to control access to the bus, requiring separate control lines between each unit and the master. A modification of this type of system uses common control lines on the bus, including a common set of priority number lines, to interconnect arbitration circuits in each unit with a permanent master unit. Any unit can request access to the bus, and when the permanent master unit releases the bus, arbitration logic in each of the units resolves which unit will gain access, putting a Hold on the bus to lock out all other units. The bus is released back to the permanent master and new access arbitration cycle is initiated. This system, in addition to requiring a permanent master unit, is relatively slow, since the arbitration process must await release of the bus to initiate a new arbitration cycle.